Design of built-in SRAM in AM-OLED display driver chip

Abstract: This paper describes a design method of a single-port SRAM circuit built in AM-OLED display driver chip, and proposes an arbitration algorithm to solve the SRAM access timing conflict problem. At the same time, a 320x240x18-bit SRAM circuit based on 0.18μm standard CMOS process is presented. The Hspice simulation results show that the dynamic power consumption of the structure can be reduced by 22.8% compared with the traditional structure.
Keywords: low power bit line structure; single port; static random accessor; arbitrator; display driver chip

0 Introduction In recent years, the advantages of low power consumption, active illumination and ultra-thin of OLED (Organic Light-Emitting Diode) have gradually replaced the trend of LCD (Light Emitting Diode), which is considered to be the fastest growing new display technology in the next 20 years. The AM-OLED (Active Drive Organic Light Emitting Diode) display driver chip that integrates functional modules such as SRAM, power supply circuit, source drive circuit, timing control and interface logic is between the mobile phone OLED screen and the MCU (microcontroller). Interface drive circuit. And its built-in SRAM is a very important module in the whole chip, which can be used to store data of one frame of image. But because it occupies most of the silicon area of ​​the entire chip, it has a decisive influence on the entire area of ​​the chip.
SRAM power consumption accounts for a large proportion of the entire chip. In recent years, there have been many studies on low-power SRAMs, in which dynamic power consumption is reduced mainly by reducing parasitic capacitance and limiting bit line voltage swing. In fact, in the case where the driver chip does not require high SRAM speed, it is feasible to sacrifice the read speed in exchange for the power consumption and area of ​​the SRAM. On the other hand, SRAM has access timing conflicts. The traditional method is to use a dual-port SRAM structure to achieve simultaneous read and write functions, but this will greatly increase the area of ​​the built-in SRAM. To this end, this paper uses time-division technology to make the single-port SRAM have the dual-port structure function, and uses the arbitration circuit to divide the priority of the two request signals to convert the external two parallel operation signals into the sequential execution of the internal single-port SRAM. So that the two request signals are completely in the independent time domain.

1 Traditional Structure of SRAM Circuit Figure 1 shows the circuit structure of a conventional six-pipe SRAM, which mainly includes a memory cell, a precharge path, a write drive, and an output circuit. Since it is a single-sided output, there is no need for a sense amplifier and a balance tube.

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When the circuit of FIG. 1 reads data, the precharge signal Prech goes low to pull the potential of the two bit lines to a high level, and the word line WL goes high, wherein one bit line is discharged to a low level through the memory cell, so that reading The output circuit is turned on, and the bit line signal is read and latched. When writing data, the precharge path also charges the two bit lines to a high level first, so that the read signal Wen opens two NMOS transistors, and the write drive circuit pulls one of the bit line potentials to a low level, and then The word line is turned on and data is written to the storage unit. Since the pre-charging circuit pre-charges the two bit lines each time during the reading and writing process, power consumption is wasted. After a detailed analysis of the circuit, this paper studies and proposes a low power bit line structure.

2 Low-Power Design of SRAM Circuits The power consumption of embedded SRAM is roughly divided into dynamic power and static power. On the specific module corresponding to the SRAM, its power consumption is mainly consumed in the decoder, word line drive, bit line precharge, sense amplifier and static leakage current. The decoder can use NAND gate logic instead of the pseudo NMOS logic design to reduce power consumption. Since this circuit structure does not have a sense amplifier circuit, there is no need to consider its power consumption. The following is mainly optimized for dynamic power consumption.
The dynamic power calculation formula of the SRAM circuit is as follows:
Where iactive is the equivalent current of the working cell; ileak is the leakage current of the inactive cell; CDE is the output node capacitance of each decoder; VINT is the internal supply voltage; iDC is the DC current consumed by the read operation; It is the activation time of DC current; CPT is the total capacitance of CMOS logic circuit and peripheral circuit; IDCP is the quiescent current of peripheral circuit. This article reduces the overall power consumption of the SRAM by reducing the parasitic capacitance of the bit line and its voltage swing.
2.1 Reducing parasitic capacitance and reducing parasitic capacitance can be done by bit line division technique (DBL) and word line division technique (DWL), which divides bit lines and word lines into multiple stages to reduce bit line parasitic capacitance and word line parasitic capacitance. It can reduce the power consumption of reading and writing, and can also improve the reading and writing speed of data, and further improve the overall performance of SRAM. Figure 2 shows the overall structure of a 320x240x18-bit SRAM memory array. The structure divides 240x18 columns into 4 blocks, each block containing 60x18 bits of data; 320 rows are divided into left and right levels, each level containing 160 lines. This divides the entire array into eight small modules, each of which is 160x60x18 bits, which reduces the wordline capacitance to a factor of 1/4. The bit line capacitance is reduced to 1/2.


2.2 Reducing the bit line voltage swing In the traditional structure, the pre-charging path of the entire read and write process will pre-charge the two bit lines, which will result in waste of power consumption. The read circuit uses a single-sided output, and the voltage swing on the bit line must be in full swing mode. Therefore, power consumption can only be reduced by reducing the voltage swing during write operation.
Figure 3 shows the block diagram of an improved SRAM using low power bit line technology. This circuit combines a single-ended output to get the circuit structure of the SRAM. The circuit differs from the conventional circuit in two ways: First, the write drive circuit uses a single-sided drive structure, and a balance tube is added to prevent data loss. In the write operation, only one bit line is pulled down to the low level to write data, and the other side bit line is floating; the second is that the precharge path is only charged during the read operation, and is not charged during the write operation.


Figure 4 shows the operation timing diagram of the new SRAM structure circuit. During the read operation, the Prech goes low, the precharge path bit line is charged to a high level, the word line goes high, the bit line BLB is discharged to a low potential through the storage tube, the read circuit reads the voltage signal on the BLB, and the data is read; In the write operation, the bit line potential is first balanced to prevent data loss. Assuming that the original storage tube stores "0" and writes data "1" to it, the write enable signal Wen first changes from low level to high level. At this time, D is high level and D' is Low level, MN1 tube is turned on, MN2 is turned off, bit line BL is left floating, bit line BLB is pulled low, word line goes high, and the transfer tube is turned on to write data "1" to the memory tube.
When the word line goes high, the bit lines BL and BLB of other cells on the same word line are charged and discharged to a certain potential through the pull-up PMOS transistor and the pull-down NMOS transistor in the memory tube. In order to prevent waste of charge and discharge of the bit line during a write operation, the pulse width of the word line selection signal can be reduced to shorten the charging time of the bit line.

3 Arbiter module design The arbiter circuit is divided into two parts: arbitration and timing generation. The arbitration part processes the read and write requests sent by the MCU and the read request signals sent by the display controller, and judges their priority levels, and then requests. The signal is fed into the timing generation circuit. The timing generation circuit is responsible for generating control signals for the sram module.
3.1 Arbiter circuit The arbiter module is mainly used to deal with the timing conflicts caused by line scan and MCU read and write. That is, when the two signals are sent at the same time, their priority is judged first, and the two external parallels are simultaneously The operational signals are converted to sequential execution of the internal single-port SRAM such that the two request signals are in a completely independent time domain of operation to reduce the area of ​​the internal SRAM. Since the MCU read/write speed is greater than the display line scan speed, the priority of the MCU read/write signal should be higher than the display read signal.
Figure 5 is a schematic diagram of the specific implementation of the arbiter. There are three request signals in the figure. The MCU read/write request signals (mcu_wr, mcu_rd) and the display data output signal (disp_ rd) are independent of each other. However, the MCU read/write request signals are not independent of each other internally, and an MCU read/write cycle corresponds to only one read or write operation. The judgment of its priority is mainly achieved by the NAND gate in Figure 5. The priority judgment method is explained below by two timing conflicts.


The arbiter first accepts an SRAM read operation request from the display control module and then receives a write request from the MCU. At this time, mcu_wr has a rising edge, the D flip-flop will latch the output high level, and the reverse direction is sent to the NAND gate through the inverter, and the NAND gate outputs a low level, so that disp_r is set to "0" to hit The read signal response is displayed until the arbitrator processes the sram_wr signal request, and then the timing generation circuit feeds back a completion signal sram_done and clears the D trigger circuit of sram_wr. Since the output signal disp of the D flip-flop that displays the read remains high, the output of the NAND gate becomes high, disp_r is reset to "1", and the interrupted disp_rd signal is reprocessed.
The second timing conflict is that the arbiter first receives the read request signal from the external MCU. When the request signal is not finished, the parallel read request signal of the display control module is sent to the arbiter. At this time, a rising edge of the request signal disp_rd causes disp to change from low level to high level. At this time, the D flip-flop output of mcu_rd is kept at a high level, and the NAND gate is not affected by the disp signal, and the output is always high. . Since the display read request signal is delayed until the MCU read request signal is processed, the clear signal is turned on, so that the D flip-flop of mcu_rd outputs a low level. At this time, the NAND gate outputs a high level, and disp_r is reset to "1". The timing generation circuit responds to its request.
3.2 Timing Generation Circuit The total request signal sram_access generated by the arbiter circuit is sent here to generate the SRAM timing control signal. The module adopts a monostable sequential circuit structure to realize its function, and the difficulty is mainly to solve the problem of generating the pre-charge signal Prech and the word line selection signal WL. According to the storage structure of the SRAM, the Prech charges the bit line only during the read operation, and does not charge during the write operation; since the pulse width of the word line select signal WL during the read operation and the write operation is different, different delay modules are required, and According to different operations, the output WL signal is selected through the transmission gate.

4 Simulation Results The built-in SRAM structure based on the 0.18μm standard CMOS process library is simulated by Hspice using the Hspice sub-module (320x60x18 bits). The total read and write current waveform is shown in Figure 6.


It can be seen from Fig. 6 that the improved structure has no large current during the write operation, and there is a partial peak current during the read operation, which is mainly because the balanced precharge bit line raises the initial voltage of the bit line, thereby reducing the precharge PMOS tube. Caused by the on resistance.
The dynamic power consumption of the improved SRAM structure is 4.6mW. If a conventional SRAM structure is used, the dynamic power consumption of the simulation for the same size circuit is 5.96mW. Therefore, the dynamic power consumption of the improved structure is reduced by 22.8% compared to the conventional structure.

5 Conclusion This paper has carried out low-power research and design on the built-in SRAM circuit in the display driver chip. The new method uses bit line division and word line division techniques to design the overall structure of the SRAM, thereby reducing parasitic capacitance. In fact, the traditional SRAM cell structure is improved in combination with low-power bit line technology, and the bit line pre-charging is stopped during the write operation, which can achieve the purpose of reducing power consumption. The introduction of an arbitration algorithm can solve the timing problem of SRAM access. The simulation results of the timing generation circuit designed according to the SRAM read and write operation requirements show that the dynamic power consumption can be greatly reduced.
At present, this circuit has been applied to an AM_OLED display driver chip and has completed pre-simulation. The simulation results can meet the expected index requirements, which proves the feasibility of the circuit.

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